CY2DP314_05 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 1:4 Differential Clock/Data Fanout Buffer

CY2DP314
1:4 Differential Clock/Data Fanout Buffer
Features
• Four ECL/PECL differential outputs
• One ECL/PECL differential or single-ended inputs
(CLKA)
• One HSTL differential or single-ended inputs (CLKB)
• Hot-swappable/-insertable
• 29 ps typical output-to-output skew
• 95 ps typical part-to-part skew
• 400 ps typical propagation delay
• 0.16 ps typical RMS phase jitter
• 7 ps typical peak period jitter
• 1.5-GHz operation (2.7-GHz maximum toggle
frequency)
• PECL and HSTL mode supply range: V_CC = 2.5V± 5% to
3.3V±5% with V_EE = 0V
• ECL mode supply range: V_{E E} = –2.5V± 5% to –3.3V±5%
with V_CC = 0V
• Industrial temperature range: –40°C to 85°C
• 20-pin SSOP package
• Temperature compensation like 100K ECL
Functional Description
The CY2DP314 is a low-skew, low propagation delay 2-to-4
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz (full
swing).
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP314 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on HSTL
or LVCMOS /LVTTL single-ended signal to four ECL/PECL
differential loads.
Since the CY2DP314 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP314 delivers consistent performance
over various platforms.
Block Diagram
VCC
CLKA
CLKA#
VEE
VCC
CLKB
CLKB#
VEE
CLK_SEL
VEE
Pin Configuration
Q0
Q0#
VCC 1
20 VCC
NC 2
19 Q0
Q1
Q1#
VCC ³
CLK_SEL ⁴
18 Q0#
17 _Q1
CLKA ⁵
16 Q1#
Q2
Q2#
CLKA# ⁶
CLKB ⁷
15 _Q2
14 _Q2#
Q3
Q3#
CLKB# ⁸
VEE ⁹
13 Q3
12 _Q3#
VCC ¹⁰
11 _VCC
20-pin SSOP
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07550 Rev.*G
Revised August 22, 2005