CY2DP3120 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 1:20 Differential Clock/Data Fanout Buffer

FastEdge™ Series
CY2DP3120
1:20 Differential Clock/Data Fanout Buffer
Features
• Twenty ECL/PECL differential outputs
• One ECL/PECL compatible differential or single-ended
clock inputs
• One HSTL compatible differential or single-ended clock
inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 1.4 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.7 GHz max. toggle frequency)
• PECL mode supply range: V_CC = 2.5V± 5% to 3.3V±5%
with V_EE = 0V
• ECL mode supply range: V_{E E} = –2.5V± 5% to –3.3V±5%
with V_CC = 0V
• Industrial temperature range: –40°C to 85°C
• 52-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6221
Block Diagram
Functional Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3120 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on
ECL/PECL signal to twenty ECL/PECL differential loads. An
external bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a
0.01-µF capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single-ended input that might
have a different self-bias point.
Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent performance
over various platforms.
Pin Configuration
VCC
CLKA
CLKA#
VEE
VCC
CLKB
CLKB#
CLK_SEL
VEE
VEE
Q0
Q0#
Q19
Q19#
VBB
VCC
VCC
CLK_SEL
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
Q19#
Q19
Q18#
Q18
52
1
51
50 49
48
47
46
45 44
43
42
41 4039
2
38
3
37
4
36
5
35
6
34
7
CY2DP3120
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Q10
Q10#
Q11
Q11#
VCC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07514 Rev.*C
Revised July 28, 2004