CY2DP1510 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 1:10 LVPECL Fanout Buffer with Selectable Clock Input

CY2DP1510
1:10 LVPECL Fanout Buffer with Selectable
Clock Input
Features
■ Select one of two low-voltage positive emitter-coupled logic
(LVPECL) input pairs to distribute to 10 LVPECL output pairs
■ 40-ps maximum output-to-output skew
■ 600-ps maximum propagation delay
■ 0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■ Up to 1.5-GHz operation
■ 32-Pin thin quad flat pack (TQFP) package
■ 2.5-V or 3.3-V operating voltage^[1]
■ Commercial and industrial operating temperature range
Logic Block Diagram
V_DD
V_SS
IN0
IN0#
IN1
IN1#
IN_SEL
100k
V_BB
Functional Description
The CY2DP1510 is an ultra-low noise, low skew,
low-propagation delay 1:10 LVPECL fanout buffer targeted to
meet the requirements of high-speed clock distribution
applications. The CY2DP1510 can select between two separate
LVPECL input clock pairs using the IN_SEL pin. The device has
a fully differential internal architecture that is optimized to
achieve low additive jitter and low skew at operating frequencies
of up to 1.5 GHz.
VDD
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-55566 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 25, 2011
[+] Feedback