CY2DL818 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 1:8 Clock Fanout Buffer

CY2DL818
1:8 Clock Fanout Buffer
Features
• Low voltage operation
• V_DD = 3.3V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVDS Outputs
• Drives either a 50-ohm or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• Packages available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at => 350 MHz – 700 Mbps
Description
This Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVDS
output pairs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock. The Cypress CY2DL818 is ideal for both
level translations from single-ended to LVDS and/or for the
distribution of LVDS-based clock signals.
The Cypress CY2DL818 has configurable input and output
functions. The input can be selectable for LVCMOS/LVTTL,
LVPECL, or LVDS signals, while the output drivers support
standard and high-drive LVDS. Drive either a 50-ohm or
100-ohm line with a single part number/device.
Block Diagram
Pin Configuration
INPUT
(LVPECL / LVDS / LVTTL)
10
INPUT A
INPUT B
11
InConfig ⁶
CNTRL ⁷
37
Q1A
36
Q1B
35
Q2A
34
Q2B
33
32
Q3A
Q3B
31
Q4A
30
Q4B
28
Q5A
27
Q5B
26
25
Q6A
Q6B
24
23
Q7A
Q7B
22
21
Q8A
Q8B
OUTPUT
(LVDS)
GND ₁
VDD 2
VDD 3
VDD 4
VDD 5
InConfig 6
CNTRL ₇
VDD ₈
GND 9
INPUT A 10
INPUT B 11
GND 12
VDD 13
VDD ₁₄
VDD ₁₅
VDD 16
VDD ₁₇
GND 18
GND 19
38 ^GND
37 ^Q1A
36 ^Q1B
35 ^Q2A
34 ^Q2B
33 ^Q3A
32 ^Q3B
31 ^Q4A
30 ^Q4B
29 ^VDD
28 ^Q5A
27 ^Q5B
26 ^Q6A
25 ^Q6B
24 ^Q7A
23 ^Q7B
22 ^Q8A
21 Q8B
20 GND
38 pin TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07058 Rev. *B
Revised December 15, 2002