CY2DL814_05 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – ComLink™ Series

Features
• Low-voltage operation
• V_DD = 3.3V
• 1:4 Fanout
• Single-input configurable for
— LVDS, LVPECL, or LVTTL
— Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• 85 ps typical output-to-output skew
• <4 ns typical propagation delay
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz – 700 Mbps
• Industrial versions available
• Packages available include TSSOP/SOIC
ComLink™ Series
CY2DL814
1:4 Clock Fanout Buffer
Description
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output functions. The input can be selectable for
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
Block Diagram
EN1
EN2
IN+
IN-
LVDS /
LVPECL /
LVTTL
CONFIG
CNTRL
Pin Configuration
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
OUTPUT
LVDS
EN1 ₁
CONFIG ₂
CNTRL ₃
VDD ₄
GND ₅
IN+ ₆
IN- ₇
EN2 8
16 Q1A
15 Q1B
14 Q2A
13 Q2B
12 Q3A
11 _Q3B
10 Q4A
9 Q4B
16-pin TSSOP/SOIC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07057 Rev. *B
Revised June 20, 2005