CY2DL15110 Datasheet, PDF(1/13 Page) Cypress Semiconductor – 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input

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CY2DL15110 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input

CY2DL15110

1:10 Differential LVDS Fanout Buffer with

Selectable Clock Input

1:10 Differential LVDS Fanout Buffer with Selectable Clock Input

Features

â Select one of two low-voltage differential signal (LVDS) input

pairs to distribute to 10 LVDS output pairs

â 40-ps maximum output-to-output skew

â 600-ps maximum propagation delay

â 0.11-ps maximum additive RMS phase jitter at 156.25 MHz

(12-kHz to 20-MHz offset)

â Up to 1.5-GHz operation

â Asynchronous output enable function

â 32-pin thin quad flat pack (TQFP) package

â 2.5-V or 3.3-V operating voltage [1]

â Commercial and industrial operating temperature range

Functional Description

The CY2DL15110 is an ultra-low noise, low skew, low

propagation delay 1:10 LVDS fanout buffer targeted to meet the

requirements of high speed clock distribution applications. The

CY2DL15110 can select between two separate LVDS input clock

pairs using the IN_SEL pin. The output enable function allows

the outputs to be asynchronously driven to a high-impedance

state. The device has a fully differential internal architecture that

is optimized to achieve low additive jitter and low skew at

operating frequencies of up to 1.5 GHz.

Logic Block Diagram

VDD

VSS

IN0

IN0#

IN1

IN1#

IN_SEL

VBB

VDD

Q0#

Q1#

Q2#

Q3#

Q4#

Q5#

Q6#

Q7#

Q8#

Q9#

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.

Cypress Semiconductor Corporation â¢ 198 Champion Court

Document Number: 001-69398 Rev. *C

â¢ San Jose, CA 95134-1709 â¢ 408-943-2600

Revised March 12, 2012

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