CY2CP1504 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input

CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
Features
■ Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
■ 30-ps maximum output-to-output skew
■ 480-ps maximum propagation delay
■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■ Up to 250 MHz operation
■ Synchronous clock enable function
■ 20-Pin thin shrunk small outline package (TSSOP) package
■ 2.5-V or 3.3-V operating voltage^[1]
■ Commercial and industrial operating temperature range
Logic Block Diagram
Functional Description
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
V_DD
V_SS
IN0
IN1
IN_SEL
CLK_EN
100k
VDD
100k
Q
D
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-56313 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 25, 2011
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