CY2CC810_06 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 1:10 Clock Fanout Buffer

CY2CC810
1:10 Clock Fanout Buffer
Features
• Low-voltage operation
• V_DD range from 2.5V to 3.3V
• 1:10 fanout
• Over voltage tolerant input hot swappable
• Drives either a 50-Ohm or 75-Ohm transmission line
• Low-input capacitance
• 250 ps typical output-to-output skew
• 19 ps typical DJ jitter
• Typical propagation delay < 3.5 ns
• High-speed operation > 500 MHz
• Industrial versions available
• Available packages include: SOIC, SSOP
Block Diagram
VDD
IN
INPUT
GND
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
OUTPUT
(AVCMOS)
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic and buffers.
The Cypress CY2CC810 fanout buffer features one input and
ten outputs. Designed for data communications clock
management applications, the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance matching and reduce noise overall.
.
Pin Configuration
IN 1
GND 2
Q1 ³
VDD ⁴
Q2 ⁵
GND ⁶
Q3 ⁷
VDD ⁸
Q4 ⁹
GND ¹⁰
20 VDD
19 Q10
18 Q9
17 _GND
16 Q8
15 _VDD
14 _Q7
13 GND
12 _Q6
11 _Q5
20 pin SOIC/SSOP
Pin Description
Pin Number
1
2, 6, 10, 13, 17
4, 8, 15, 20
3, 5, 7, 9, 11, 12, 14, 16, 18, 19
Pin Name
IN
GND
V_DD
Q1... Q10
Description
Input
LVCMOS
Ground
Power
Power Supply
Power
Output
AVCMOS
Cypress Semiconductor Corporation
Document #: 38-07056 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised September 5, 2006