CY2CC1810 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 1:10 Clock Fanout Buffer with Output Enable

COMLINK™ SERIES
CY2CC1810
1:10 Clock Fanout Buffer with Output Enable
Features
• Low-voltage operation
• V_DD range from 2.5 to 3.3V
• 1:10 fanout
• Drives either a 50-ohm or 75-ohm transmission line
• Over voltage tolerant input hot swappable
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• High-speed operation > 200 MHz
• LVTTL-/LVCMOS-compatible input
— Output disable to three-state
• Industrial versions available
• Packages available include: SOIC/SSOP
Block Diagram
Description
The Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1810 fanout buffer features one input and
ten three-state outputs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance-matching and eliminate the need for series-
damping resistors; they also reduce noise overall.
Pin Configuration
OE#
VDD
IN
GND
Pin Description
Pin Number
1,7,8,12,13,17,20,24
3,10,15,22
5
6
2,4,9,11,14,16,18,19,21,23
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
OUTPUT (AVCMOS)
Pin Name
G_ND
V_DD
OE#
IN
Q10........Q1
GND 1
Q10 2
VDD 3
Q9 4
OE# ₅
IN ₆
GND ₇
GND ₈
Q8 ₉
VDD ₁₀
Q7 ₁₁
GND ₁₂
24 GND
23 Q1
22 VDD
21 ^Q2
20 ^GND
19 ^Q3
18 ^Q4
17 ^GND
16 ^Q5
15 ^VDD
14 ^Q6
13 ^GND
24 pin SOIC/SSOP
Pin Description
Ground
Power
Power Supply
Power
Output Enable
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Output
AVCMOS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07055 Rev. *C
Revised December 14, 2002