CY29973 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 3.3V 125-MHz Multi-Output Zero Delay Buffer

CY29973
3.3V 125-MHz Multi-Output Zero Delay Buffer
Features
• Output Frequency up to 125 MHz
• 12 Clock Outputs: Frequency Configurable
• 350-ps max. Output to Output Skew
• Configurable Output Disable
• Two Reference Clock Inputs for Dynamic Toggling
• Oscillator or PECL Reference Input
• Spread Spectrum Compatible
• Glitch-free Output Clocks Transitioning
• 3.3V Power Supply
• Pin Compatible with MPC973
• Industrial Temp. Rang: –40°C to +85°C
• 52-Pin TQFP Package
Table 1. Frequency Table^[1]
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F_VC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
TCLK0 ₀
TCLK1 1
TCLK_SEL
FB_IN
Phase
Detector
VCO
0
1
LPF
FB_SEL2
DQ
Sync
Frz
DQ
Sync
Frz
MR#/OE
Power-On
Reset
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
0
/2 1
SCLK
SDATA
Output Disable ₁₂
Circuitry
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
INV_CLK
Note:
1. x = the reference input frequency, 200 MHz < F_VCO < 480 MHz.
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7 _CY29973 33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07291 Rev. *B
Revised January 19, 2004