CY29972_12 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 3.3 V, 125-MHz Multi-Output Zero Delay Buffer

CY29972
3.3 V, 125-MHz Multi-Output
Zero Delay Buffer
3.3 V, 125-MHz Multi-Output Zero Delay Buffer
Features
■ Output frequency up to 125 MHz
■ 12 Clock outputs: frequency configurable
■ 350 ps max. output-to-output skew
■ Configurable output disable
■ Two reference clock inputs for dynamic toggling
■ Oscillator or crystal reference input
■ Spread-spectrum-compatible
■ Glitch-free output clocks transitioning
■ 3.3 V power supply
■ Pin-compatible with MPC972
■ Industrial temperature range: –40 °C to +85 °C
■ 52-pin thin quad flat package (TQFP) package
Block Diagram
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
TCLK0 ₀
TCLK1 1
TCLK_SEL
FB_IN
Phase
Detector
VCO
0
1
LPF
FB_SEL2
Table 1. Frequency Table ^[1]
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F_VC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
DQ
Sync
Frz
DQ
Sync
Frz
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
MR#/OE
Power-On
Reset
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
0
/2 1
SCLK
SDATA
Output Disable
Circuitry
12
INV_CLK
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
QC0
QC1
QC2
QC3
FB_OUT
SYNC
Note
1. x = the reference input frequency, 200 MHz < F_VCO < 480 MHz.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07290 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 11, 2011
[+] Feedback