CY29962 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer

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CY29962
2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer
Features
• 2.5V or 3.3V operation
• Output frequency up to 150MHz
• Supports PowerPC ^® and Pentium^® processors
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output skew < 150 ps
Table 1. Frequency Table^[1]
SELA
0
1
QA
VCO/2
VCO/4
SELB
0
1
QB
VCO/2
VCO/4
• Split 2.5V/3.3V outputs
• Spread-spectrum-compatible
• Glitch-free output clocks transitioning
• Output disable control
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin TQFP package
SELC
0
1
QC
VCO/2
VCO/4
FB_SEL
0
1
FB_OUT
VCO/8
VCO/12
Block Diagram
Pin Configuration
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
FB_IN
SELA
SELB
AVDD
PLL
0
0
/2
/4
REF
1
1
/8
FB
/12
A
0
DQ
1
B
0
1
DQ
SELC
C
0
1
DQ
OE#
FB_SEL
FB
0
1
DQ
0
1
48 47 46 45 44 43 42 41 40 39 38 37
2
3
VSS ¹
36 ^VSSA
4
TCLK ²
5
PECL_CLK ³
PECL_CLK# ⁴
35 ^FB_OUT
34 ^QB0
33 ^QB1
6
0
VDD ⁵
REF_SEL ⁶
CY29962
32 ^VDDB
31 ^QB2
1
FB_SEL ⁷
AVDD ⁸
30 ^QB3
29 ^VSSB
2
SELA ⁹
28 ^QB4
3
SELB ¹⁰
27 ^QB5
4
SELC ¹¹
26 ^QB6
5
VSSC ¹²
25 ^VDDB
13 14 15 16 17 18 19 20 21 22 23 24
6
0
1
2
3
4
5
6
FB_OUT
Note:
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1) or 25 MHz to 50 MHz (FB_SEL = 0).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07364 Rev. *B
Revised December 26, 2002