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CY29948 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer | |||
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CY29948
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
Features
⢠2.5V or 3.3V operation
⢠200-MHz clock support
⢠LVPECL or LVCMOS/LVTTL clock input
⢠LVCMOS-/LVTTL-compatible inputs
⢠12 clock outputs: drive up to 24 clock lines
⢠Synchronous Output Enable
⢠Output three-state control
⢠250 ps max. output-to-output skew
⢠Pin compatible with MPC948, MPC948L, MPC9448
⢠Available in Commercial and Industrial temp. range
⢠32-pin TQFP package
Description
The CY29948 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The 12 outputs are LVCMOS or LVT-
TL compatible and can drive 50⦠series or parallel terminated
transmission lines. For series terminated transmission lines,
each output can drive one or two traces giving the device an
effective fanout of 1:24. The outputs can also be three-stated
via the three-state input TS#. Low output-to-output skews
make the CY29948 an ideal clock distribution buffer for nested
clock trees in the most demanding of synchronous systems.
The CY29948 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
0
1
Pin Configuration
VDDC
12 Q0-Q11
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
24
2
23
3
22
4
5
CY29948
21
20
6
19
7
18
8
17
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose ⢠CA 95134 ⢠408-943-2600
Document #: 38-07288 Rev. *B
Revised December 22, 2002
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