CY29943 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer

CY29943
2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer
Features
• 200-MHz clock support
• 2.5V or 3.3V operation
• LVPECL clock input
• LVCMOS-/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 200 ps max. output-to-output skew
• Output Enable control
• Pin compatible with MPC942P
• Available in Industrial and Commercial
• 32-pin LQFP package
Description
The CY29943 is a low-voltage 200-MHz clock distribution
buffer with an LVPECL-compatible input clock. All other control
inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs
are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can
drive 50Ω series or parallel terminated transmission lines. For
series terminated transmission line, each output can drive one
or two traces giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29943 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Block Diagram
PECL_CLK
PECL_CLK#
OE
Pin Configuration
VDD
18 _Q0-Q17
VSS
VSS
OE
NC
PECL_CLK
PECL_CLK#
VDD
VDD
1
24 Q6
2
23 Q7
3
22 Q8
4
5
CY29943
21
20
VDD
Q9
6
19 Q10
7
18 Q11
8
17 VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07285 Rev. *C
Revised December 21, 2002