CY29940_11 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer 200-MHz clock support

2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer
Features
■ 200-MHz clock support
■ LVPECL or LVCMOS/LVTTL clock input
■ LVCMOS/LVTTL compatible inputs
■ 18 clock outputs: drive up to 36 clock lines
■ 60 ps typical output-to-output skew
■ Dual or single supply operation:
❐ 3.3 V core and 3.3 V outputs
❐ 3.3 V core and 2.5 V outputs
❐ 2.5 V core and 2.5 V outputs
■ Pin compatible with MPC940L, MPC9109
■ Available in Commercial and Industrial temperature
■ 32-pin LQFP package
Block Diagram
VDD
PECL_CLK
PECL_CLK#
0
TCLK
1
TCLK_SEL
CY29940
2.5 V or 3.3 V, 200-MHz,
1:18 Clock Distribution Buffer
Description
The CY29940 is a low-voltage 200-MHz clock distribution buffer
with the capability to select either a differential LVPECL or a
LVCMOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The eighteen outputs are 2.5 V or 3.3 V
LVCMOS/LVTTL compatible and can drive 50  series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces giving
the device an effective fanout of 1:36. Low output-to-output
skews make the CY29940 an ideal clock distribution buffer for
nested clock trees in the most demanding of synchronous
systems.
VDDC
18 _Q0-Q17
Pin Configuration
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
24
2
23
3
22
4
5
CY29940
21
20
6
19
7
18
8
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07283 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2011
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