CY29940-1 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer

Features
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 150 ps max. output-to-output skew
• 23Ω output impedance
• Dual or single supply operation:
— 3.3V core and 3.3V outputs
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
• Pin-compatible with MPC940L, MPC9109
• Available in commercial and industrial temperature
ranges
• 32-pin TQFP package
Block Diagram
CY29940-1
2.5V or 3.3V, 200-MHz
1:18 Clock Distribution Buffer
Description
The CY29940-1 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL-
or a LVCMOS/LVTTL-compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are
LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V
or 3.3V LVCMOS/LVTTL-compatible and can drive 50Ω series
or parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29940-1 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Pin Configuration
VDD
PECL_CLK
PECL_CLK#
0
TCLK
1
TCLK_SEL
VDDC
18 _Q0-Q17
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
32 31 30 29 28 27 26 25
1
24 Q6
2
23 ^Q7
3
22 Q8
4 _{CY29940-1 21} VDD
5
20
Q9
6
19 Q10
7
18 ^Q11
8
17 ^VSS
9 10 11 12 13 14 15 16
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07487 Rev. **
Revised January 28, 2003