CY29775 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer

CY29775
2.5V or 3.3V, 200-MHz, 14 Output Zero
Delay Buffer
Features
■ Output frequency range: 8.3 MHz to 200 MHz
■ Input frequency range: 4.2 MHz to 125 MHz
■ 2.5V or 3.3V operation
■ Split 2.5V/3.3V outputs
■ 14 Clock outputs: Drive up to 28 clock lines
■ 1 Feedback clock output
■ 2 LVCMOS reference clock inputs
■ 150 ps max output-output skew
■ PLL bypass mode
■ Spread Aware™
■ Output enable/disable
■ Industrial temperature range: –40°C to +85°C
■ 52-Pin 1.0-mm TQFP package
Description
The CY29775 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
The CY29775 features two reference clock inputs and provides
14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A
and Bank B divide the VCO output by 4 or 8 while Bank C divides
by 8 or 12 per SEL(A:C) settings, see Function Table (Bank A,
B, and C) on page 4. These dividers allow output to input ratios
of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS
compatible output can drive 50Ω series or parallel terminated
transmission lines. For series terminated transmission lines,
each output can drive one or two traces giving the device an
effective fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 8.3 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback divider,
see Frequency Table on page 4.
When PLL_EN is LOW, PLL is bypassed and the reference clock
directly feeds the output dividers. This mode is fully static and the
minimum input clock frequency specification does not apply.
Block Diagram
V C O _ S E L (1 ,0 )
PLL_EN
TCLK_SEL
TCLK0
TCLK1
F B _ IN
SELA
SELB
SELC
CLK_STP#
FB_SEL(1,0)
M R #/O E
PLL
200 -
500MHz
÷2
÷2 / ÷4
CLK
STOP
÷4
÷2 / ÷4
CLK
STOP
÷4 / ÷6
CLK
STOP
÷4 / ÷6 / ÷8 / ÷12
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
QC0
QC1
QC2
QC3
FB_OUT
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07480 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 19, 2007
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