CY29774 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer

774
CY29774
2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
Features
• Output frequency range: 8.3 MHz to 125 MHz
• Input frequency range: 4.2 MHz to 62.5 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 14 Clock outputs: Drive up to 28 clock lines
• 1 Feedback clock output
• 2 LVCMOS reference clock inputs
• 150 ps max output-output skew
• PLL bypass mode
• Spread Aware™
• Output enable/disable
• Pin compatible with MPC9774
• Industrial temperature range: –40°C to +85°C
• 52-Pin 1.0-mm TQFP package
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
Block Diagram
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see Functional
Table. These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
TCLK1
F B _ IN
SELA
SELB
SELC
CLK_STP#
FB_SEL(1,0)
M R #/O E
PLL
200 -
500MHz
÷2
÷4
÷2 / ÷4
CLK
STOP
÷2 / ÷4
CLK
STOP
÷4 / ÷6
CLK
STOP
÷4 / ÷6 / ÷8 / ÷12
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
QC0
QC1
QC2
QC3
F B _O U T
VSS
M R #/O E
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
VDD
AVDD
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7 _CY29774 33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VSS
QB1
VDDQB
QB2
VSS
QB3
VDDQB
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07479 Rev. **
Revised April 28, 2003