CY29773 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

CY29773
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
• Output frequency range: 8.33 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max Output duty cycle variation
• 12 Clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: LVPECL or LVCMOS
• 300-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9773 and MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.0-mm TQFP package
Block Diagram
Description
The CY29773 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29773 features one LVPECL and two LVCMOS
reference clock inputs and provides 12 outputs partitioned in
three banks of four outputs each. Each bank divides the VCO
output per SEL(A:C) settings (see Table 2. Function Table
(Configuration Controls)). These dividers allow output-to-input
ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4,
1:1, and 5:6. Each LVCMOS-compatible output can drive 50Ω
series- or parallel-terminated transmission lines. For
series-terminated transmission lines, each output can drive
one or two traces, giving the device an effective fanout of 1:24.
The PLL is ensured stable, given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies, from 8 MHz to 200 MHz. For normal
operation, the external feedback input FB_IN is connected to
the feedback output FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see Table 1. Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
TCLK0
0
TCLK1
1
TCLK_SEL
FB_IN
Phase
Detector
VCO
0
1
LPF
FB_SEL2
MR#/OE
Power-On
Reset
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
0
/2 1
Output Disable
12
Circuitry
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
AV SS
MR# /O E
SCLK
SDA TA
FB _ S EL 2
PL L _ EN
REF_SEL
TCL K _ S EL
TCL K 0
TCL K 1
PECL _ CL K
PECL _ CL K #
A V DD
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
C Y 29773 ³³
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
V SS
QB0
V DDQB
QB1
V SS
QB2
V DDQB
QB3
FB_IN
V SS
FB_OUT
V DD
FB_SEL0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07573 Rev. **
Revised August 27, 2003