CY29352_08 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer

CY29352
2.5V or 3.3V, 200 MHz,
11 Output Zero Delay Buffer
Features
■ Output frequency range: 16.67 MHz to 200 MHz
■ Input frequency range: 16.67 MHz to 200 MHz
■ 2.5V or 3.3V operation
■ Split 2.5V and 3.3V outputs
■ ±2% maximum output duty cycle variation
■ 11 clock outputs: drive up to 22 clock lines
■ LVCMOS reference clock input
■ 125 ps maximum output-output skew
■ PLL bypass mode
■ Spread Aware™
■ Output enable and disable
■ Pin compatible with MPC9352 and MPC952
■ Industrial temperature range: –40°C to +85°C
■ 32-pin 1.4 mm TQFP package
Description
The CY29352 is a low voltage high performance 200 MHz PLL
based zero delay buffer designed for high speed clock distri-
bution applications.
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in three banks of five, four, and
two outputs. Bank A divides the VCO output by four and six
while bank B divides by four and two, and bank C divides by
two and four per SEL(A:C) settings, see Table 3 on page 3.
These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1,
2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output drives one or two
traces, giving the device an effective fanout of 1:22.
The PLL is stable if the VCO is configured to run between 200
MHz to 500 MHz. This allows a wide range of output
frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO runs at multiples of the
input reference clock set by the feedback divider, see Table 2
on page 3. When PLL_EN# is HIGH, PLL is bypassed and the
reference clock directly feeds the output dividers. This mode
is fully static and the minimum input clock frequency specifi-
cation does not apply.
Block Diagram
PLL_EN#
REFCLK
Phase
VCO
÷4 /
Detector 200-500MHz
÷2
÷6
FB_IN
LPF
VCO_SEL
SELA
÷4 /
÷2
SELB
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
SELC
MR/OE#
÷2 /
QC0
÷4
QC1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07476 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 14, 2008
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