CY29352 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer

CY29352
Features
• Output frequency range: 16.67 MHz to 200 MHz
• Input frequency range: 16.67 MHz to 200 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max Output duty cycle variation
• 11 Clock outputs: Drive up to 22 clock lines
• LVCMOS reference clock input
• 125-ps max output-output skew
• PLL bypass mode
• Spread Aware
• Output enable/disable
• Pin compatible with MPC9352 and MPC952
• Industrial temperature range: –40°C to +85°C
• 32-Pin 1.0mm TQFP package
2.5V or 3.3V, 200-MHz, 11-Output
Zero Delay Buffer
Description
The CY29352 is a low voltage high performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in 3 banks of 5, 4, and 2
outputs. Bank A divides the VCO output by 4 or 6 while Bank
B divides by 4 and 2 and Bank C divides by 2 and 4 per
SEL(A:C) settings, see Function Table. These dividers allow
output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3.
Each LVCMOS compatible output can drive 50Ω series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:22.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see
Table 1.
When PLL_EN# is HIGH, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
PLL_EN#
REFCLK
Phase
VCO
÷4 /
Detector 200-500MHz
÷2
÷6
FB_IN
LPF
VCO_SEL
SELA
÷4 /
÷2
SELB
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
Pin Configuration
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
1
24 VSS
2
23 QB1
3
22 QB0
CY29352 ⁴
21 VDDQB
5
20 VDDQA
6
19 QA4
7
18 QA3
8
17 VSS
SELC
MR/OE#
÷2 /
QC0
÷4
QC1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07476 Rev. **
Revised March 19, 2003