CY28401 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 100-MHz Differential Buffer for PCI Express and SATA

CY28401
100-MHz Differential Buffer for PCI Express and SATA
Features
Functional Description
• CK409 or CK410 companion buffer
• Eight differential 0.7v clock pairs
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STOP# power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable
• 48-pin SSOP package
The CY28401 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
OE_[0:7]
SRC_STOP#
PWRDWN#
SCLK
SDATA
SRC_DIV2#
PLL/BYPASS#
SRCT_IN
SRCC_IN
HIGH_BW#
Output
Control
SMBus
Controller
Output
Buffer
DIV
PLL
DIFT0
DIFC0
DIFT1
DIFC1
DIFT2
DIFC2
DIFT3
DIFC3
DIFT4
DIFC4
DIFT5
DIFC5
DIFT6
DIFC6
DIFT7
DIFC7
LOCK
Pin Configuration
SRC_DIV2# 1
VDD 2
VSS 3
SRCT_IN 4
SRCC_IN 5
OE_0 6
OE_3 7
DIFT0 8
DIFCO 9
VSS 10
VDD 11
DIFT1 12
DIFC1 13
OE_1 14
OE_2 15
DIFT2 16
DIFC2 17
VSS 18
VDD 19
DIFT3 20
DIFC3 21
PLL/BYPASS# 22
SCLK 23
SDATA 24
48 VDD_A
47 VSS_A
46 IREF
45 LOCK
44 OE_7
43 OE_4
42 DIFT7
41 DIFC7
40 VSS
39 VDD
38 DIFT6
37 DIFC6
36 OE_6
35 OE_5
34 DIFT5
33 DIFC5
32 VSS
31 VDD
30 DIFT4
29 DIFC4
28 HIGH_BW#
27 SRC_STOP#
26 PWRDWN#
25 VSS
48 SSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07592 Rev. **
Revised November 24, 2003