CY28358 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 200-MHz Differential Clock Buffer/Driver

58
PRELIMINARY
CY28358
200-MHz Differential Clock Buffer/Driver
Features
Description
• Up to 200 MHz operation
• Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize the
outputs to the clock input
• Conforms to the DDR1 specification
• Spread Aware™ for EMI reduction
• 28-pin SSOP package
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the feed-
back clock FBIN.
The two line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test purpos-
es.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low–jitter output differential clocks.
Block Diagram
Pin Configuration
SCLK
SDATA
CLKIN
FBIN
AVDD
10
Serial
Interface
Logic
PLL
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
FBOUT
CLKC0 1
CLKT0 2
VDD 3
CLKT1 ₄
CLKC1 5
GND 6
SCLK ₇
CLKIN ₈
NC ₉
AVDD ₁₀
AGND 11
VDD ₁₂
CLKT2 ₁₃
CLKC2 ₁₄
28 GND
27 CLKC5
26 CLKT5
25 CLKC4
24 ^CLKT4
23 ^VDD
22 ^SDATA
21 ^NC
20 ^FBIN
19 ^FBOUT
18 ^NC
17 ^CLKT3
16 ^CLKC3
15 ^GND
28 pin SSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07417 Rev. *A
Revised December 14, 2002