CY28343 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – Zero Delay SDR/DDR Clock Buffer

CY28343
Zero Delay SDR/DDR Clock Buffer
Features
• Phase-lock loop clock distribution for DDR and SDR
SDRAM applications
• One-single-end clock input to 6 pairs DDR outputs or
13 SDR outputs.
• External feedback pins FBIN_SDR/FBOUT_SDR are
used to synchronize the outputs to the clock input for
SDR.
• External feedback pins FBIN_SDR/FBOUT_SDR are
used to synchronize the outputs to the clock input for
DDR.
• SMBus interface enables/disables outputs.
• Conforms to JEDEC SDR/DDR specifications
• Low jitter, low skew
• 48 pin SSOP package
Table 1. Function Table
SELDDR_SDR#
1= DDR Mode
0 = SDRAM Mode
CLKIN
2.5V
Compatible
3.3V
Compatible
SDRAM(0:12)
OFF
Active
3.3V
Compatible
DDRT/C(0:5)
Active
2.5V
Compatible
OFF
FBIN_DDR
2.5V
Compatible
OFF
FBOUT_DDR
Active
2.5V
Compatible
OFF
FBIN_SDR FBOUT_SDR
OFF
OFF
Active
3.3V
Compatible
Active
3.3V
Compatible
Block Diagram
Pin Configuration^[1]
SCLK
SDATA
Control
Logic
VDD_3.3V
CLKIN
FBIN_DDR
*SELDDR_SDR
FBIN_SDR
PLL
VDD_2.5V
FBOUT_DDR
DDRT(0:5)
DDRC(0:5)
VDD_3.3V
FBOUT_SDR
SDRAM (0:12)
VDD_3.3V 1
SDRAM0 2
SDRAM1 3
SDRAM2 4
SDRAM3 5
VSS 6
VDD_3.3V 7
SDRAM4 8
SDRAM5 9
CLKIN 10
SDRAM6 11
SDRAM7 12
VSS 13
VDD_3.3V 14
SDRAM8 15
SDRAM9 16
SDRAM10 17
SDRAM11 18
VSS 19
VDD_3.3V 20
SDRAM12 21
FBOUT_SDR 22
FBIN_SDR* 23
VSS 24
Note:
1. Pins marked with [*] have internal pull-down resistors. Pins marked with [**] have internal pull-up resistors.
48 SELDDR_SDR#*
47 FBIN_DDR*
46 FBOUT_DDR
45 VDD_2.5V
44 DDRT5
43 DDRC5
42 DDRT4
41 DDRC4
40 VSS
39 VDD_2.5
38 DDRT3
37 DDRC3
36 DDRT2
35 DDRC2
34 VSS
33 VDD_2.5V
32 DDRT1
31 DDRC1
30 DDRT0
29 DDRC0
28 VSS
27 VDD_3.3V
26 SCLK**
25 SDATA**
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07369 Rev. *A
Revised December 26, 2002