CY28331 Datasheet, PDF (1/17 Pages) SpectraLinear Inc – Clock Generator for AMD™ Hammer

CY28331
Clock Generator for AMD™ Hammer
Features
• Supports AMD™ Hammer CPU
• Two differential pairs of CPU clocks
• Eight low-skew/low-jitter PCI clocks
• One free-running PCI clock
• Four low-skew/low-jitter PCI/HyperTransport™ clocks
• One 48M output for USB
• One programmable 24M or 48M for FDC
• Three REF 14.318-MHz clocks
• Dial-a-Frequency^ programmability
• Lexmark Spread Spectrum for optimal electromagnetic
interference (EMI) reduction
• SMBus register-programmable options
• 5V-tolerance SCLK and SDATA lines
• 3.3V operation
• Power management control pins
• 48-pin SSOP package
Block Diagram
Table 1. Frequency Table (MHz)^[1]
FS PCI_HT
(3:0) SEL
CPU
HT66
PCI
0000
X High-Z
(All outputs except XOUT are three-stated)
0001
0/1
133.9
67.0/33.5
33.5
0010
0/1
166.9
66.8/33.4
33.4
0011
0/1
200.9
67.0/33.5
33.5
0100
0/1
100.0
66.7/33.3
33.3
0101
0/1
133.3
66.7/33.3
33.3
0110
0/1
166.7
66.7/33.3
33.3
0111
0/1
200.0
66.7/33.3
33.3
(default)
1000
0/1
105.0
70.0/35.0
35.0
1001
0/1
110.0
73.3/36.7
36.7
1010
0/1
210.0
70.0/35.0
35.0
1011
0/1
240.0
60.0/30.0
30.0
1100
0/1
270.0
67.5/33.8
33.8
1101
0/1
233.3
58.3/29.2
29.2
1110
0/1
266.7
66.7/33.3
33.3
1111
0/1
300.0
75.0/37.5
37.5
Pin Configuration
XIN
XOUT
14.31818MHz
XTAL
/4
PLL1
/2
SEL#
FS(0:3)
PCISTOP#
SPREAD
PD#
SCLK
SDATA
Control
Logic
PLL2
/N
STOP
CNTL
REF(0:2)
USB
24_48MHz
SRESET#
CPUT(0:1)
CPUC(0:1)
PCI33_F
PCI33_(0:7)
*FS0/REF0
VDD
XIN
XOUT
VSS
PCI33HT66_0/*PCI33HT66SEL0#
PCI33HT66_1/*PCI33HT66SEL1#
PCI33_HT66_2
VDD
VSS
PCI33_HT66_3
PCI33_7
PCI33_0
PCI33_1
VSS
VDD
PCI33_2
PCI33_3
VDD
VSS
PCI33_4
PCI33_5
PCISel/PCI33_F
*PCI33_6/PCISTOP#
1
48 *FS1/REF1
2
47 VSS
3
46 VDD
4
45 *FS2/REF2
5
44 SRESET#/PD#
6
43 VDDA
7
42 VSSA
8
41 CPUT0
9
40 CPUC0
10
39 VSS
11
38 VDD
12
37 CPUT1
13
36 CPUC1
14
35 VDD
15
34 VSS
16
33 VSSF
17
32 VDDF
18
31 **USB/FS3
19
30 VSS
20
29 VDD
21
28 24_48MHz/**SEL#
22
27 VSS
23
26 SDATA
24
25 SCLK
*100K Internal Pull-up
**100K Internal Pull-down
PCI33_HT66_(0:3)
Note:
1. HCLK, 66 MHz, and 33 MHz are in phase and synchronous at power-up.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07491 Rev. *E
Revised April 14, 2005