CY28312B-2 Datasheet, PDF (1/17 Pages) SpectraLinear Inc – FTG for VIA™ K7 Series Chipset with Programmable Output Frequency

CY28312B-2
FTG for VIA™ K7 Series Chipset with
Programmable Output Frequency
Features
• Single-chip FTG solution for VIA™ K7 Series chipsets
• Programmable clock output frequency with less than
1-MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW-selected or
SW-programmed clock frequency when Watchdog
timer time-out
• Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for PCI output clocks
• Programmable output skew between CPU, AGP and PCI
• Maximized electromagnetic interference (EMI)
suppression using Cypress’s Spread Spectrum
technology
• Low jitter and tightly controlled clock skew
• Two pairs of differential CPU clocks
• Eleven copies of PCI clocks
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• Three copies of 14.31818-MHz reference clocks
• One RESET output for system recovery
• Power management control support
Key Specifications
CPU outputs cycle-to-cycle jitter: ............................... 250 ps
48-MHz, 3V66, PCI outputs
cycle-to-cycle jitter: ..................................................... 250 ps
CPU 3V66 output skew:.............................................. 200 ps
48-MHz output skew: .................................................. 250 ps
PCI output skew:......................................................... 500 ps
Block Diagram
X1
X2
SDATA
SCLK
(FS0:4)
XTAL
OSC
PLL REF FREQ
SMBus
Logic
Divider,
Delay,
and
Phase
Control
Logic
PD#
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
PLL 1
PLL2
/2
SEL24_48#*
VDD_REF
REF2
REF1/FS1*
REF0/FS0*
VDD_CPU
CPUT0,CPUC0
2
CPUT_CS,CPUC_CS
VDD_AGP
AGP0:2
3
VDD_PCI
PCI0/SEL24_48#*
PCI1:8
5
PCI9_E
RST#
VDD_48MHz
48MHz/FS3*
24_48MHz/FS4*
[1]
Pin Configuration
VDD_REF 1
GND_REF 2
X1 3
X2 4
VDD_48MHz 5
*FS2/48MHz 6
*FS3/24_48MHz 7
GND_48MHz 8
*FS4/PCI_F 9
*SEL24_48#/PCI0 10
PCI1 11
GND_PCI 12
PCI2 13
PCI3 14
VDD_PCI 15
PCI4 16
PCI5 17
PCI6 18
GND_PCI 19
PCI7 20
PCI8 21
PCI9_E 22
VDD_PCI 23
RST# 24
48 REF0/FS0*
47 REF1/FS1*
46 REF2
45 REF_STOP#*
44 AGP_STOP#*
43 GND_CPU
42 CPUT0
41 CPUC0
40 VDD_CPU
39 CPUT_CS
38 CPUC_CS
37 GND_CPU
36 CPU_STOP#*
35 PCI_STOP#*
34 PD#*
33 VDD_CORE
32 GND_CORE
31 SDATA
30 SCLK
29 GND_AGP
28 AGP2
27 AGP1
26 AGP0
25 VDD_AGP
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07596 Rev. **
Revised December 1, 2003