CY27C256 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 32K x 8-Bit CMOS EPROM

1CY 27C2 56
fax id: 3013
CY27C256
32K x 8-Bit CMOS EPROM
Features
• Wide speed range
— 45 ns to 200 ns (commercial and military)
• Low power
— 248 mW (commercial)
— 303 mW (military)
• Low standby power
— Less than 83 mW when deselected
• ±10% Power supply tolerance
Functional Description
The CY27C256 is a high-performance 32,768-word by 8-bit
CMOS EPROM. When disabled (CE HIGH), the CY27C256
automatically powers down into a low-power stand-by mode.
The CY27C256 is packaged in the industry standard 600-mil
DIP, PLCC, and TSOP packages. The CY27C256 is also avail-
able in a CerDIP package equipped with an erasure window
to provide for reprogrammability. When exposed to UV light,
the EPROM is erased and can be reprogrammed. The mem-
ory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY27C256 offers the advantage of lower power and su-
perior performance and programming yield. The EPROM cell
requires only 12.5V for the super voltage, and low current re-
quirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each EPROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet both DC and AC specification limits.
Reading the CY27C256 is accomplished by placing active
LOW signals on OE and CE. The contents of the memory location
addressed by the address lines (A₀ - A₁₄) will become available on
the output lines (O₀ - O₇).
Logic Block Diagram
A₁₄
A₁₃
A₁₂
A₁₁
A10
ROW
ADDRESS
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
A9
A₈
A₇
ADDRESS
A₆
DECODER
A5
A₄
A₃
COLUMN
A₂
ADDRESS
A₁
A₀
POWER–DOWN
CE
OE
Pin Configurations
O₇
DIP/Flatpack
LCC/PLCC^[1]
O₆
V_PP 1
28 VCC
A₁₂ 2
27 A14
4 3 2 1 32 3130
O5
O₄
A7 3
26 A13
A₆ 4
25 A8
A₅ 5
24 A9
A₄ 6 ^27C25623 A₁₁
A₃ 7
22 OE
A_{6 5}
A_{5 6}
A_{4 7}
A_{3 8}
A2 ₉
A_{1 10}
27C256
29 ^A8
28 ^A9
27 ^A11
26 NC
25 OE
24 ^A10
A2 8
21 A10
A0 ₁₁
23 CE
O3
A1 9
A₀ 10
20 CE
19 O₇
NC 12
22 O7
O0 13
21 O₆
14151617 181920
O₀ 11
18 O6
O₁ 12
17 O5
O2
O₂ 13
16 O₄
GND 14
15 O3
27c256–3
27c256–2
O₁
O0
27c256–1
Note:
1. For PLCC only: Pins 1 and 17 are common and tied to the die attach pad. They must therefore be DU (don’t use) for the PLCC package.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 1993 – Revised August 1994