CY26580 Datasheet, PDF (1/5 Pages) Cypress Semiconductor – PacketClock™ Network Applications Clock

Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
CY26580
PacketClock™
Network Applications Clock
Benefits
• Internal PLL with precision operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Frequency Table
Part Number Outputs
CY26580-1
2
Input Frequency
125MHz or 25-MHz driven
Output Frequencies
100 MHz, 133.33 MHz
Logic Block Diagram
CLK
OSC.
Q
Φ
VCO
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
133.33 MHz
100 MHz
SEL_25
SEL_CLK
Pin Configuration
CY26580
20-pin SSOP (QSOP)
NC ₁
NC ₂
CLK ₃
VDD 4
NC 5
GND ₆
NC ₇
NC ₈
NC ₉
133 MHz 10
20 ^NC
19 SEL_CLK
18 NC
17 100 MHz
16 _VDD
15 NC
14 _GND
13 _NC
12 _NC
11 _{SEL_25}
VDD VDD GND GND
Input Select Options
SEL_25
X
0
1
SEL_CLK
0
1
1
Input Type
Driven
Driven
Input Frequency
CLK1
Do not use
125
133.33
25
133.33
CLK2
100
100
Unit
MHz
MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07536 Rev. *B
Revised June 03, 2004