CY26200 Datasheet, PDF (1/5 Pages) Cypress Semiconductor – T1/E1 Clock Generator

PRELIMINARY
CY26200
T1/E1 Clock Generator
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
Part Number Outputs
CY26200
1
Input Frequency Range
19.44 MHz
Logic Block Diagram
Benefits
High-performance PLL tailored for T1/E1 clock generation
Meets critical timing requirements in complex system designs
Enables application compatibility
Output Frequencies
1.544 MHz/2.048 MHz (selectable)
19.44 XIN
XOUT
OSC
Q
Φ
VCO
P
PLL
AVDD AVSS VDD VSS
OUTPUT
DIVIDERS
CLK1
Pin Configuration
CY26200
8-pin SOIC
XIN 1
AVDD 2
FS 3
AVSS 4
8 XOUT
7 VSS
6 CLK1
5 _VDD
Table 1: CY26200 Frequency Select Option
Frequency Select
0
1
CLK1
1.544
2.048
Unit
MHz
MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07335 Rev. *A
Revised December 14, 2002