CY26049-22 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – FailSafe™ PacketClock™ Global Communications Clock Generator

CY26049-22
FailSafe™ PacketClock™
Global Communications Clock Generator
Features
Benefits
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• 100-MHz output from 10-MHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• 16-lead TSSOP
• Integrated high-performance PLL tailored for telecommuni-
cations frequency synthesis eliminates the need for external
loop filter components
• When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Works with commonly available, low-cost 10-MHz crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm² footprint and
a height profile of just 1.1 mm
Logic Block Diagram
input reference
(10M Hz)
IC L K
external pullable crystal
(10M Hz)
X IN
XOUT
F A ILS A F E^TM
CONTROL
D IG IT A L
CONTROLLED
CRYSTAL
O SCILLATOR
PHASE
LOCKED
LOOP
OUTPUT
D IV ID E R
CLKA
100M H z
SAFE
ICLK detected
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07730 Rev. **
Revised January 12, 2005