CY25561_13 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Spread Spectrum Clock Generator

CY25561
Spread Spectrum Clock Generator
Features
■ 50 to 166 MHz operating frequency range
■ Wide range of spread selections: 9
■ Accepts clock and crystal inputs
■ Low power dissipation
❐ 70 mW- Typ at 66 MHz
■ Frequency spread disable function
■ Center spread modulation
■ Low cycle-to-cycle jitter
■ 8-pin SOIC Package
Functional Description
CY25561 is a spread spectrum clock generator (SSCG) IC used
to reduce electromagnetic Interference (EMI) found in today’s
high speed digital electronic systems.
CY25561 uses a Cypress proprietary phase-locked loop (PLL)
and spread spectrum clock (SSC) technology to synthesize and
frequency modulate the input frequency of the reference clock.
Logic Block Diagram
By doing this, the measured EMI at the fundamental and
harmonic frequencies of clock (SSCLK) is reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
CY25561 is a very simple and versatile device to use. The
frequency and spread percentage range is selected by
programming S0 and S1 digital inputs. These inputs use three
logic states including high (H), low (L), and middle (M) logic
levels to select one of the nine available spread percentage
ranges. Refer to Table 1 for programming details.
CY25561 is intended for use with applications with a reference
frequency in the range of 50 to 166 MHz.
A wide range of digitally selectable spread percentages is made
possible by using tri-level (high, low, and middle) logic at the S0
and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
CY25561 is available in an eight-pin SOIC package with a 0 °C
to 70 °C operating temperature range.
Xin/
CLK
1
300 K
REFERENCE
DIVIDER
PD CP
Loop
Filter
Xout 8
MODULATION
CONTROL
FEEDBACK
DIVIDER
vco
VDD ₂
VSS ₃
INPUT
DECODER
LOGIC
VDD
20K
VDD
20K
DIVIDER
&
MUX
20K
20K
VSS
VSS
5
67
SSCC
S1 S0
Note: Refer to the CY25560 data sheet for operation at frequencies from 25 to100 MHz
4 SSCLK
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07242 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 26, 2013