CY25100_08 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – Field and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction

CY25100
Field and Factory-Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
■ Wide operating output (SSCLK) frequency range
❐ 3 MHz to 200 MHz
■ Programmable spread spectrum with nominal 31.5 kHz
modulation frequency
❐ Center spread: ±0.25% to ±2.5%
❐ Down spread: –0.5% to –5.0%
■ Input frequency range
❐ External crystal: 8 to 30 MHz fundamental crystals
❐ External reference: 8 to 166 MHz clock
■ Integrated phase-locked loop (PLL)
■ Field programmable
❐ CY25100SCF and CY25100SIF, 8-pin SOIC
❐ CY25100ZCF and CY25100ZIF, 8-pin TSSOP
■ Programmable crystal load capacitor tuning array
■ Low cycle-to-cycle jitter
■ 3.3V operation
■ Commercial and industrial operation
■ Spread spectrum on/off function
■ Power down or Output Enable function
Benefits
■ Services most PC peripherals, networking, and consumer
applications.
■ Provides wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC) require-
ments. Reduces development and manufacturing costs and
time-to-market.
■ Eliminates the need for expensive and difficult to use higher
order crystals.
■ Internal PLL to generate up to 200 MHz output. Able to generate
custom frequencies from an external crystal or a driven source.
■ In-house programming of samples and prototype quantities is
available using the CY3672 programming kit and
CY3690 (TSSOP) or CY3691 (SOIC) socket adapter.
Production quantities are available through Cypress’s value
added distribution partners or by using third party programmers
from BP Microsystems, HiLo Systems, and others.
■ Enables fine tuning of output clock frequency by adjusting
C_Load of the crystal. Eliminates the need for external C_Load
capacitors.
■ Suitable for most PC, consumer, and networking applications.
■ Application compatibility in standard and low power systems.
■ Ability to enable or disable spread spectrum with an external
pin.
■ Enables low power state or output clocks to High-Z state.
Logic Block Diagram
3
XIN
2
XOUT
4
PD# or OE
8
SSON#
RFB
C X IN
CXOUT
PLL
with
M O D U L ATIO N
CONTROL
P R O G R AM M AB L E
CONFIGURATION
1
VDD
5
VSS
OUTPUT
DIVIDERS
and
MUX
6
REFCLK
7
SSCLK
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07499 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2008
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