CY24272_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – Rambus XDR™ Clock Generator with Zero SDA Hold Time

CY24272
Rambus^ XDR™ Clock Generator with
Zero SDA Hold Time
Rambus‚ XDR™ Clock Generator with Zero SDA Hold Time
Features
■ Meets Rambus^ Extended Data Rate (XDR™) clocking
requirements
■ 25 ps typical cycle-to-cycle jitter
❐ –135 dBc/Hz typical phase noise at 20 MHz offset
■ 100 or 133 MHz differential clock input
■ 300–667 MHz high speed clock support
■ Quad (open drain) differential output drivers
■ Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
■ Spread Aware™
■ 2.5 V operation
■ 28-pin TSSOP package
Table 1. Device Comparison
CY24271
SDA hold time = 300 ns
(SMBus compliant)
R_RC = 200  typical
(Rambus standard drive)
CY24272
SDA hold time = 0 ns
(I²C compliant)
R_RC = 295  minimum
(Reduced output drive)
Logic Block Diagram
/BYPASS
EN
Bypass
MUX
REFCLK,REFCLKB
PLL
EN
RegA
EN
RegB
EN
RegC
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
SDA
ID0
ID1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42414 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 17, 2011
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