CY24271 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – Rambus® XDR™ Clock Generator

CY24271
Rambus^® XDR™ Clock Generator
Features
■ Meets Rambus^® Extended Data Rate (XDR™) clocking
requirements
■ 25 ps typical cycle-to-cycle jitter
❐ 135 dBc/Hz typical phase noise at 20 MHz offset
■ 100 or 133 MHz differential clock input
■ 300–800 MHz high speed clock support
■ Quad (open drain) differential output drivers
■ Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
■ Spread Aware™
■ 2.5V operation
■ 28-pin TSSOP package
Logic Block Diagram
/B YPA SS
EN
EN
RegA
Bypass
MUX
REFCLK,REFC LKB
PLL
EN
RegB
EN
RegC
EN
RegD
SCL
SDA
ID 0
ID 1
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00411 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 23, 2007
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