CY24207 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – MediaClock PDP Clock Generator

CY24207
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with Analog Adjust
• 3.3V operation
MediaClock™
PDP Clock Generator
Benefits
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Large ±200-ppm range, better linearity
• Enables application compatibility
Part Number Outputs
CY24207-1
4
CY24207-2
4
Input Frequency
27-MHz Crystal Input
27-MHz Crystal Input
Output Frequency Range
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/67.357642 MHz (frequency selectable)
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/68.400599 MHz (frequency selectable)
Block Diagram
XIN
XOUT
VCXO
OSC.
Q
Φ
VCO
P
PLL
FS0
FS1
OE
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CLK1
CLK2
REFCLK1
REFCLK2
Pin Configuration
16-pin TSSOP
XIN ¹
VDD 2
AVDD 3
VCXO 4
AVSS 5
VSSL 6
REFCLK2 ₇
REFCLK1 8
16 ^XOUT
15 OE
14 FS1
13 VSS
12 _CLK1
11 VDDL
10 _FS0
9 _CLK2
VDDL
VDD AVDD AVSS VSS ^VSSL
Frequency Select Options
OE FS1 FS0
CLK1/CLK2 (-1)^[1]
0
0
0
off
0
0
1
off
0
1
0
off
0
1
1
off
1
0
0
54
1
0
1
53.946053 (–1 ppm)
1
1
0
67.425
1
1
1
67.357642 (3.8 ppm)
Note:
1. “off” = output is driven high.
CLK1/CLK2 (-2)^[1]
off
off
off
off
54
53.946053 (–1 ppm)
67.425
68.400599(–8.8 ppm)
REFCLK 1/2
27
27
27
27
27
27
27
27
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07553 Rev. *A
Revised July 31, 2003