CY24206 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – MediaClock - TM DTV, STB Clock Generator

CY24206
MediaClock™ DTV, STB Clock Generator
Features
Benefits
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
• Available in 16-pin TSSOP Package
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Part Number
CY24206-1
CY24206-2
CY24206-3
CY24206-4
Outputs
3
4
4
4
Input Frequency
Output Frequency Range
27 MHz
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
27 MHz
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
27 MHz
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
27 MHz
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
OSC.
Q
Φ
VCO
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
FS0
FS1
FS2
OE
Pin Configurations
CY24206-1
16-pin TSSOP
VDDL VDD
XIN ¹
VDD 2
AVDD 3
OE 4
AVSS 5
VSSL 6
CLK1 7
CLK2 8
16 ^XOUT
15 FS2
14 FS1
13 VSS
12 _N/C
11 VDDL
10 _FS0
9 _REFCLK
AVDD AVSS VSS VSSL
CY24206-2,3,4
16-pin TSSOP
XIN ¹
VDD 2
AVDD 3
OE 4
AVSS 5
VSSL 6
CLK1 7
CLK2 8
16 ^XOUT
15 FS2
14 FS1
13 VSS
12 _CLK3
11 VDDL
10 _FS0
9 _REFCLK
CLK1
CLK2
REFCLK
CLK3 (-2, -3,-4)
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07451 Rev. *B
Revised September 27, 2004