CY24204 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – MediaClock™ DTV, STB Clock Generator

Features
• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• VCXO with Analog Adjust
• 3.3V operation
Part Number Outputs
Input Frequency
CY24204-3
4 27-MHz Crystal Input
CY24204-4
4 27-MHz Crystal Input
CY24204-5
4 27-MHz Crystal Input
CY24204
MediaClock™
DTV, STB Clock Generator
Benefits
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Large ±150-ppm range, better linearity
• Enables application compatibility
Output Frequency Range
Two copies of 27-MHz reference clock output, two copies of
27/27.027/74.250/74.17582418 MHz (frequency selectable)
Two copies of 27-MHz reference clock output, two copies of
27/27.027/74.250/74.17582418 MHz (frequency selectable,
Increased VCXO pull range)
Two copies of 27-MHz reference clock output, two copies of
27/27.027/74.250/74.17582418 MHz (frequency selectable,
Increased output drive strength)
Block Diagram
XIN
XOUT
VCXO
OSC.
Q
Φ
VCO
P
PLL
FS0
FS1
OE
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CLK1
CLK2
REFCLK1
REFCLK2
(-3,-4,-5)
Pin Configurations
16-pin TSSOP
XIN ¹
VDD 2
AVDD 3
VCXO 4
AVSS 5
VSSL 6
REFCLK2 7
REFCLK1 8
16 ^XOUT
15 OE
14 FS1
13 VSS
12 _CLK1
11 VDDL
10 _FS0
9 _CLK2
VDDL
VDD AVDD AVSS VSS ^VSSL
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07450 Rev. *C
Revised January 19, 2005