CY241V08A-41 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – MPEG Clock Generator with VCXO

CY241V08A-41
MPEG Clock Generator with VCXO
Features
Benefits
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
• Highest-performance PLL tailored for multimedia applica-
tions
• Meets critical timing requirements in complex system
designs
• Application compatibility for a wide variety of designs
Frequency Table
VCXO Control
Part Number Outputs Input Frequency Range Output Frequencies
Curve
Other Features
CY241V08A-41
1 27-MHz pullable crystal input One copy of 27 MHz linear
per Cypress specification One copy of 83.33 MHz
(non-pullable)
Pinout-compatible with
MK3741
Block Diagram
54 REF
PLL
27 XIN
XOUT
OSC
VCXO
Pin Configuration
CY241V08A-41
8-pin SOIC
XIN ¹
VDD 2
VCXO 3
VSS 4
8 XOUT
7 REF
6 _{83.33 MHz}
5 _{XBUF/27 MHz}
VDD VSS
OUTPUT
DIVIDER
83.33MHz
XBUF/27MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07655 Rev. *A
Revised April 22, 2004