CY241V08A-11 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – MPEG Clock Generator with VCXO

CY241V08A-11
MPEG Clock Generator with VCXO
Features
Benefits
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
• Highest-performance PLL tailored for multimedia applica-
tions
• Meets critical timing requirements in complex system
designs
• Application compatibility for a wide variety of designs
Table 1. Frequency Table
Part Number
CY241V08A-11
Outputs Input Frequency Range
Output
VCXO Control
Frequencies
Curve
Other Features
1 13.5-MHz pullable crystal input One copy of 54 MHz linear
per Cypress specification
Pinout-compatible with
CY2411
Block Diagram
13.5 XIN
XOUT
OSC
VCXO
PLL
VDD VSS
OUTPUT
DIVIDER
54 MHz
Pin Configuration
CY241V08A-11
8-pin SOIC
XIN ¹
VDD 2
VCXO 3
VSS 4
8 XOUT
7 VSS
6 _54MHz
5 _VDD
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07654 Rev. *A
Revised April 22, 2004