CY24130 Datasheet, PDF (1/5 Pages) Cypress Semiconductor – HOTLink SMPTE Receiver Training Clock

CY24130
HOTLink II™ SMPTE Receiver Training Clock
Features
• Integrated phase-locked loop
• Low-jitter, high-accuracy outputs
• 3.3V operation
Benefits
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Part Number Outputs
CY24130-1
2
CY24130-2
2
Input Frequency
27 MHz (Driven Reference)
27 MHz (Crystal Reference)
Output Frequency Range
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
OSC.
Q
Φ
VCO
P
PLL
S0
S1
S2
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CLKA
REFCLK
VDDL VDD AVDD AVSS VSS VSSL
Pin Configuration
CY24130-1, -2
16-pin TSSOP
XIN ¹
VDD 2
AVDD 3
S0 4
AVSS 5
VSSL 6
N/C 7
CLKA 8
16 ^XOUT
15 S2
14 REFCLK
13 VSS
12 _N/C
11 VDDL
10 _S1
9 _N/C
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07711 Rev. **
Revised February 04, 2005