CY23S09_04 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – Low-Cost 3.3V Spread Aware™ Zero Delay Buffer

CY23S09
CY23S05
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
• Zero input-output propagation delay
• Multiple low-skew outputs
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY23S05)
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
• Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium^-based systems
• Test Mode to bypass PLL (CY23S09 only, see Select
Input Decoding table on page 2)
• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
• 3.3V operation, advanced 0.65µ CMOS technology
• Spread Aware™
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
REF
S2
S1
PLL
MUX
Select Input
Decoding
CY23S09
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw (for commercial temper-
ature devices) and 25.0 µA (for industrial temperature
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
The CY23S05/CY23S09 is available in two different configu-
rations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
Pin Configuration
SOIC/TSSOP/SSOP
Top View
REF
1
CLKA1 2
CLKA2
3
V_DD
4
GND
5
CLKB1 ⁶
CLKB2
7
S2
8
16 _CLKOUT
15
CLKA4
14
CLKA3
13
V_DD
12
GND
11
CLKB4
10
CLKB3
9
S1
CY23S09
REF
PLL
CY23S05
CLKOUT
CLK1
CLK2
CLK3
CLK4
SOIC
Top View
REF ¹
CLK2 ²
CLK1 ³
GND ⁴
8 CLKOUT
7 CLK4
6 V_DD
5 CLK3
CY23S05
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07296 Rev. *C
Revised September 21, 2004