CY23S02_12 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – Spread Aware™, Frequency Multiplier, and Zero Delay Buffer

CY23S02
Spread Aware™, Frequency Multiplier,
and Zero Delay Buffer
Features
■ Spread Aware™ — designed to work with SSFTG reference
signals
■ 90 ps typical jitter OUT2
■ 200 ps typical jitter OUT1
■ 65 ps typical output-to-output skew
■ 90 ps typical propagation delay
■ Voltage range: 3.3 V ± 5%, or 5 V ± 10%
■ Output frequency range: 20 MHz - 133 MHz
■ Two outputs
■ Configuration options allow various multiplication of the
reference frequency, refer to Table 1 to determine the
specific option which meets your multiplication needs
■ Available in 8-pin SOIC package
Block Diagram
FBIN
External feedback connection to
OUT1 or OUT2, not both
FS0
÷Q
FS1
Table 1. Configuration Options
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0 FS1
OUT1
0
0
2 X REF
1
0
4 X REF
0
1
REF
1
1
8 X REF
0
0
4 X REF
1
0
8 X REF
0
1
2 X REF
1
1
16 X REF
OUT2
REF
2 X REF
REF/2
4 X REF
2 X REF
4 X REF
REF
8 X REF
Pin Configuration
FBIN
1
IN
2
GND
3
FS0
4
8
OUT2
7
VDD
6
OUT1
5
FS1
IN
Reference
Input
Phase
Detector
Charge
Pump
Loop
Filter
Output
Buffer
VCO
÷2
Output
Buffer
OUT1
OUT2
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07155 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 8, 2011