CY23FP12-002_11 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 200-MHz Field Programmable Zero Delay Buffer

CY23FP12-002
200-MHz Field Programmable Zero
Delay Buffer
Features
■ Pre-programmed configuration
■ Fully field-programmable
❐ Input and output dividers
❐ Inverting/noninverting outputs
❐ Phase-locked loop (PLL) or fanout buffer configuration
■ 10 MHz to 200 MHz operating range
■ Split 2.5-V or 3.3-V outputs
■ Two low-voltage complementary metal oxide semiconductor
(LVCMOS) reference inputs
■ Twelve low-skew outputs
❐ Output-output skew < 200 ps
❐ Device-device skew < 500 ps
■ Input-output skew < 250 ps
■ Cycle-cycle jitter < 100 ps (typical)
■ Three-stateable outputs
■ Less than 50 μA shutdown current
■ Spread Aware™
■ 28-pin shrunk small outline package (SSOP)
■ 3.3-V operation
Functional Description
The CY23FP12-002 is a pre-programmed version of the
CY23FP12. It features a high-performance fully field-program-
mable 200-MHz zero delay buffer designed for high-speed clock
distribution. The integrated PLL is designed for low jitter and
optimized for noise rejection. These parameters are critical for
reference clock distribution in systems using high-performance
ASICs and microprocessors.
The CY23FP12-002 is fully programmable through volume or
prototype programmers, enabling the user to define an
application-specific zero delay buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in Table 2
on page 5, and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
enables the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon. The
CY23FP12-002 also features a proprietary auto power down
circuit that shuts down the device in case of a REF failure,
resulting in less than 50 μA of current draw.
The CY23FP12-002 provides 12 outputs grouped in two banks
with separate power supply pins which can be connected
independently to either a 2.5 V or a 3.3 V rail.
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source when
REFSEL is asserted/deasserted.
Logic Block Diagram
VDDC
Lock Detect
REFSEL
REF1
REF2
FBK
÷M
100 to
÷1
400MHz
÷N
PLL
÷2
÷3
÷4
÷X
÷2X
Function
S[2:1] ^Selection
VSSC
Test Logic
VDDA
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
CLKA5
VSSA
VDDB
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
CLKB5
VSSB
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07644 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2011
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