CY23EP09_11 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 2.5 V or 3.3 V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer

CY23EP09
2.5 V or 3.3 V, 10-220 MHz, Low Jitter,
9-Output Zero Delay Buffer
Features
■ 10 MHz to 220 MHz maximum operating range
■ Zero input-output propagation delay, adjustable by loading on
CLKOUT pin
■ Multiple low-skew outputs
— 45 ps typical output-output skew
— One input drives nine outputs, grouped as 4 + 4 + 1
■ 25 ps typical cycle-to-cycle jitter
■ 15 ps typical period jitter
■ Standard and High drive strength options
■ Available in space-saving 16-pin 150-mil small outline
integrated circuit (SOIC) or 4.4-mm thin shrunk small outline
package (TSSOP) packages
■ 3.3 V or 2.5 V operation
■ Industrial temperature available
Functional Description
The CY23EP09 is a 2.5 V or 3.3 V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC or
TSSOP package. The -1H version operates up to 220 (200) MHz
frequencies at 3.3 V (2.5 V), and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input clock
on the REF pin. The phase-locked loop (PLL) feedback is
on-chip and is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 4. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the input
clock to be directly applied to the outputs for chip and system
testing purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 A of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves like a non-zero delay buffer in this mode, and the
outputs are not tri-stated.
The CY23EP09 is available in different configurations, as shown
in the Ordering Information table. The CY23EP09-1 is the base
part. The CY23EP09-1H is the high-drive version of the -1, and
its rise and fall times are much faster than the -1.
These parts are not intended for 5 V input-tolerant applications
Block Diagram
REF
S2
S1
PLL
MUX
Select Input
Decoding
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07760 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 1, 2011
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