CY2305_11 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – Low Cost 3.3-V Zero Delay Buffer

CY2305, CY2309
Low Cost 3.3-V Zero Delay Buffer
Features
■ Not recommended for new designs. The CY2305C and
CY2309C are form, fit, function compatible devices with
improved specifications.
■ 10 MHz to 100/133 MHz operating range, compatible with CPU
and PCI bus frequencies
■ Zero input-output propagation delay
■ 60-ps typical cycle-to-cycle jitter (high drive)
■ Multiple low skew outputs
❐ 85 ps typical output-to-output skew
❐ One input drives five outputs (CY2305)
❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
■ Compatible with Pentium-based systems
■ Test Mode to bypass phase-locked loop (PLL) (CY2309)
■ Packages:
❐ 8-pin, 150-mil SOIC package (CY2305)
❐ 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
■ 3.3-V operation
■ Commercial and industrial temperature ranges
Logic Block Diagram
Functional Description
The CY2309 is a low-cost 3.3-V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five low
skew clocks. The -1H versions of each device operate at up to
100-/133 MHz frequencies, and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can be
controlled by the select inputs as shown in “Select Input
Decoding for CY2309” on page 4. If all output clocks are not
required, BankB can be three-stated. The select inputs also
allow the input clock to be directly applied to the outputs for chip
and system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode when
there are no rising edges on the REF input. In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25.0 μA current draw for these parts. The CY2309 PLL
shuts down in one additional case as shown in “Select Input
Decoding for CY2309” on page 4.
Multiple CY2305 and CY2309 devices can accept the same input
clock and distribute it. In this case, the skew between the outputs
of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two or three different
configurations, as shown in “Ordering Information for CY2305”
on page 13. The CY2305-1/CY2309-1 is the base part. The
CY2305-1H/ CY2309-1H is the high-drive version of the -1, and
its rise and fall times are much faster than the -1.
REF
S2
S1
PLL
MUX
Select Input
Decoding
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number : 38-07140 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 28, 2011
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