CY2303 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Phase-Aligned Clock Multiplier

CY2303
Phase-Aligned Clock Multiplier
Features
Functional Description
• 3-multiplier configuration (1x, 2x, 4x Ref)
• 10 MHz to 166.67 MHz operating range (reference input
from 10 MHz to 41.67 MHz)
• Phase Alignment
• 80 ps typical period jitter
• Output enable pin
• 3.3V operation
• 5V Tolerant input
• 8-pin 150-mil SOIC package
• Commercial and Industrial Temperature available
The CY2303 is a 3 output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows user to obtain 1x, 2x, and 4x Ref output
frequencies on respective output pins.
The CY2303 has an on-chip PLL, which locks to an input clock
presented on the REFIN pin. The PLL feedback is internally
connected to the REF output. The input-to-output skew is
guaranteed to be less than ±200 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
Multiple CY2303 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
The CY2303 is available in commercial and industrial temper-
ature ranges.
Selector Guide
Part Number
CY2303SC,
CY2303SXC
CY2303SI,
CY2303SXI
Outputs
3
3
Input Frequency Range
10 MHz–41.67 MHz
Output Frequency Range
10 MHz–166.67 MHz
10 MHz–41.67 MHz
10 MHz–166.67 MHz
Specifics
Commercial Temperature
Industrial Temperature
Block Diagram
FBK
REFIN
x1
PLL
x2
x4
OE
REF
REFx2
REFx4
Pin Configuration
8-pin SOIC
Top View
REF ¹
GND ²
REFIN ³
N/C 4
8 OE
7 V_DD
6 REFx4
5 REFx2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07249 Rev. *B
Revised August 2, 2005