CY23020-3 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 10-output, 400-MHz LVPECL Zero Delay Buffer

CY23020-3
10-output, 400-MHz LVPECL Zero Delay Buffer
Features
• 400-ps max Total Timing Budget (TTB) window
• 10 LVPECL outputs
• 1 LVPECL differential input
• Selectable output frequency range from 100 to 400 MHz
• Multiply by 2 option
• 15-ps RMS Cycle-Cycle Jitter
• Power-down mode
• Lock indicator
• 3.3V power supply
• Available in 48-pin QFN package
Overview
TheCY23020-3 is a high-performance 400-MHz LVPECL
Output phase-locked loop (PLL)-based zero delay buffer
(ZDB) designed for high- speed clock distribution applications.
The device features a guaranteed TTB window specifying all
occurrences of output clocks with respect to the input
reference clock across variations in voltage, temperature,
process, frequency, and ramp rate.
Additionally, the CY23020-3 can be used as a fan-out buffer
via the S[1:2] control pins. In this mode, the PLL is bypassed
and the reference clock is routed to the output buffers.
Block Diagram
Pin Configurations
REF+
REF-
FBIN+
FBIN-
LOCK
÷^1/÷²
÷¹
PLL
÷2
S1:2
RANGE
MUL
Control
Logic
FBOUT+
FBOUT-
Q1+
Q1-
Q2+
Q2-
Q3+
Q3-
Q4+
Q4-
Q5+
Q4-
Q6+
Q6-
Q7+
Q7-
Q8+
Q8-
Q9+
Q9-
1 FBOUT-
2 _GND
3 _Q1-
4 Q1+
5 VDD
6 Q2+
7 Q2-
8 GND
9 _Q3-
10 Q3+
11 _VDD
12 Q4+
48 47 46
FV F
BD B
OD I
U
N
T
+
+
45 44 43
FN L
BC O
I
C
N
K
-
42 41 40
VGR
DN E
DD F
CC -
39 38 37
RVQ
E D9
F D+
+
CY23020-3
Q9- 36
GND 35
Q8- 34
Q8+ 33
VDD 32
Q7+ 31
Q7- ₃₀
GND 29
QG S SM R
4 N 2 1U A
-D
LN
G
E
13 14 15 16 17 18
GV V GGQ
ND D NN5
DD D DD-
CC C C
19 20 21 22 23 24
Q6- 28
Q6+ 27
VDD 26
Q5+ 25
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07473 Rev. *A
Revised June 5, 2003