CY2300_08 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – Phase-Aligned Clock Multiplier

Features
■ 4-multiplier configuration
■ Single phase-locked loop architecture
■ Phase Alignment
■ Low jitter, high accuracy outputs
■ Output enable pin
■ 3.3V operation
■ 5V Tolerant input
■ Internal loop filter
■ 8-pin 150-mil SOIC package
■ Commercial Temperature
Logic Block Diagram
REFIN
/2
OE
CY2300
Phase-Aligned Clock Multiplier
Benefits
■ 1/2x, 1x, 1x, 2x Ref
■ 10 MHz to 166.67 MHz operating range (reference input from
20 MHz to 83.33 MHz)
■ All outputs have a consistent phase relationship with each other
and the reference input
■ Meets critical timing requirements
■ Enables design flexibility and lower power
consumption
■ Supports industry standard design platforms
■ Allows flexibility on Reference input
■ Alleviates the need for external components
■ Industry standard packaging saves on board space
■ Suitable for wide spectrum of applications
FBK
PLL
Divider
Logic
1/2xREF
REF
REF
2xREF
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07252 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 23, 2008
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