CY2300 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Phase-Aligned Clock Multiplier

CY2300
Features
• 4-multiplier configuration
• Single phase-locked loop architecture
• Phase Alignment
• Low jitter, high accuracy outputs
• Output enable pin
• 3.3V operation
• 5V Tolerant input
• Internal loop filter
• 8-pin 150-mil SOIC package
• Commercial and Industrial Temperature available
Selector Guide
Part Number
CY2300SC
CY2300SI
Outputs
4
4
Input Frequency Range
20 MHz–83.33 MHz
20 MHz–83.33 MHz
Phase-Aligned Clock Multiplier
Benefits
• 1/2x, 1x, 1x, 2x Ref
• 10 MHz to 166.67 MHz operating range (reference input
from 20 MHz to 83.33 MHz)
• All outputs will have a consistent phase relationship
with each other and the reference input
• Meets critical timing requirements
• Enables design flexibility and lower power
consumption
• Supports industry standard design platforms
• Allows flexibility on Reference input
• Alleviates the need for external components
• Industry standard packaging saves on board space
• Suitable for wide spectrum of applications
Output Frequency Range
10 MHz–166.67 MHz
10 MHz–166.6 7MHz
Specifics
Commercial Temperature
Industrial Temperature
Block Diagram
FBK
REFIN
/2
PLL
OE
Divider
Logic
1/2xREF
REF
REF
2xREF
Pin Configuration
8-pin SOIC
Top View
1/2xREF ¹
GND ²
REFIN ³
REF ⁴
8 ^OE
7 ^VDD
6 2xREF
5 ^REF
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07252 Rev. *B
Revised July 26, 2004