CY2283 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs

PRELIMINARY
CY2283
Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for
Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium® /II, Cyrix 6x86,
and AMD K6 processor-based motherboards
— Four CPU clocks at 2.5V or 3.3V
— Twelve 3.3V SDRAM clocks^[1]
— Five synchronous PCI clocks, one free-running
— One 3.3V 48 MHz USB clock
— One 3.3V Ref. clock at 14.318 MHz
— Two AGP clocks at 3.3V
• Support for ALI (-1 option) and VIA (-2 option)
• I²C™ Serial Configuration Interface
• Full EMI control with factory-EPROM programmable
output drive and slew rate
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Power-down, CPU stop, and PCI stop pins
• Available in space-saving 48-pin SSOP package
Functional Description
The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,
or AMD processor-based PCs using the ALI Aladdin V (-1 op-
tion) or VIA MVP3 (-2 option) chipset.
The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There
are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI
clocks is free-running. Additionally, the part outputs twelve
3.3V SDRAM clocks^[1], one 3.3V USB clock at 48 MHz, and
one 3.3V reference clock at 14.318 MHz. Finally, the part out-
puts two AGP clocks running at 66.66 MHz or 60 MHz.
The CY2283 has the flexibility to work as either a one-chip or
as part of a two-chip clocking solution. In 100-MHz board de-
signs based on the ALI Aladdin V chipset, it is recommended
that the CY2283 be used with an external SDRAM buffer so-
lution such as the CY2318NZ or CY2314NZ. In this configura-
tion the SDRAM outputs on the CY2283 must be either turned
off using I²C or left floating. The CY231xNZ family provides the
SDRAM outputs in place of the CY2283 and can be placed in
close proximity to the SDRAM modules.
The CY2283 possesses power-down, CPU stop, and PCI stop
pins for power management control. These inputs are multi-
plexed with SDRAM clock outputs, and are selected when the
MODE pin is driven LOW. Additionally, the signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
The CY2283 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2283 Selector Guide
Clock Outputs
-1 (ALI V) -2 (VIA MVP3)
CPU (66.6, 75, 83.3, 100MHz)
SDRAM
PCI (30, 33.3 MHz)
USB (48MHz)
AGP (66.6, 60MHz)
Ref. (14.318 MHz)
CPU-PCI delay
AGP clock
4
12^[1]
5^[2]
1
2
1
2.5−5.5 ns
In phase
with PCI
4
12
5^[2]
1
2
1
2.5−5.5 ns
In phase
with CPU
Notes:
1. SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the
ALI V chipset, an external CY231xNZ buffer should be used.
2. One free-running PCI clock
Logic Block Diagram
XTALIN
14.318
MHz
XTALOUT
OSC.
CPU
PLL
STOP
LOGIC
SEL0
SEL1
MODE
SCLK
SDATA
EPROM
SYS PLL
Delay (-2 option)
/1, /1.25, /1.5
Delay (-1 option)
/2
SERIAL
INTERFACE
CONTROL
LOGIC
STOP
LOGIC
REF0 (14.318 MHz)
CPUCLK [0-3]
V_DDCPU
SDRAM5/PWR_DWN
SDRAM [0-4],[8-11]
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AGP
PCI [0-3]
PCICLK_F
USBCLK
Pin Configuration (48 SSOP)
AV_{DD 1}
REF0 2
V_SS 3
XTALIN 4
XTALOUT 5
V_{DDQ3 6}
PCICLK_F ₇
PCICLK0 8
V_{SS 9}
PCICLK1 10
PCICLK2 11
PCICLK3 12
AGP0 13
V_{DDQ3 14}
AGP1 15
V_SS 16
SDRAM11 17
SDRAM10 18
V_DDQ3 19
SDRAM9 20
SDRAM8 21
V_{SS 22}
SDATA 23
SCLK 24
48
V_DDQ3
47 USBCLK
46 _SEL1
45 V_SS
44 CPUCLK0
43 CPUCLK1
42
V_DDCPU
41 CPUCLK2
40 CPUCLK3
39 V_SS
38 SDRAM0
37 SDRAM1
36
V_DDQ3
35 SDRAM2
34 _SDRAM3
33 V_SS
32 _SDRAM4
31 SDRAM5/PWR_DWN
30
V_DDQ3
29 SDRAM6/CPU_STOP
28 SDRAM7/PCI_STOP
27
V_SS
26 SEL0
25 MODE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 12, 1998